Universal programmable logic device in the inverte

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Universal programmable logic device in the inverter control circuit of

Flexibility in the actual situation of the line configuration, which simplify board design and improve the electromagnetic compatibility is very favorable. (2) All external logic is encapsulated within the PLD, security is better. The F240 does not have any security features, the use of PLD to the hardware circuit, so that the design of the control system to maintain the confidentiality to be the most convenient methods. (3) The vast majority of logic functions and pin can be achieved through the PLD programming,[link widoczny dla zalogowanych], so that circuit theory, circuit boards and control software can be before, and independent of the specific design of the external logic, to avoid waste, reduce The purpose of cost and efficiency, which in the design, testing, trial and experimental stage small quantities is very attractive. (4) the use of PLD can easily design complex functions (including multiple levels of protection described above, and dead-time compensation) and improve system reliability and efficiency of software running. The dead time compensation,[link widoczny dla zalogowanych], for example,[link widoczny dla zalogowanych], using PLD to achieve hardware compensation software than the average of each switching cycle takes less computing time of about 2s, which is considerable high-frequency inverter. Figure 3 for the use of PLD to achieve the dead time compensation CL0CKPwM the occurrence and timing of instruction dead or door IIpx Figure 3 dead time using PLD to achieve the logical principle of compensation for the occurrence and Fig. 3kcalprincipleofPLD-Baseddeadtimegenerationandcompensation logical principle [which CLOCK,[link widoczny dla zalogowanych], Ipx, Vgxl and Vgx2 were working the clock, phase current polarity signal, the bridge arm and leg IG-BT under the control pulses. Figure 4 is the use of dead time compensation PLD to achieve the experimental results (switching frequency of 3kHz, dead-time 20s). Experimental results show that the results are quite satisfactory. r ● ● ● J Pat / 'Wn-,' compensation for the former 'factory √ compensation before' (a) the output frequency of 5Hz (b) output frequency 25Hz (50ms/div) (1Oms/div) Figure 4 using PLD to achieve the dead time Compensation results Fig. 4ExperimentalresultsofPLD-Baseddeadtimecompensation (Lower: beforecompensation,[link widoczny dla zalogowanych], Upper: aftercompensation) 3 Conclusion of programmable logic devices can be used not only to better take into account the universal inverter reliability, small size, low cost, high performance, and many other increasing demands, but also enable the control circuit design to be flexible and efficient, to improve the development, production and maintenance efficiency are also of great help.